1. Technical Field
Methods for manufacturing a magnetic random access memory (abbreviated as ‘MRAM’) are disclosed. More specifically, improved methods for manufacturing a MRAM are disclosed which improve a process margin and prevent damage to the MRAM during the manufacturing process to allow a facile manufacturing process of the MRAM which has a higher speed than a SRAM, integration density as high as a DRAM, and the properties of a nonvolatile memory such as a flash memory.
2. Description of the Related Art
Most of the semiconductor memory manufacturing companies have developed the MRAM which uses a ferromagnetic material as one of the next generation memory devices.
The MRAM is a memory device for reading and writing information wherein multi-layer ferromagnetic thin films is used by sensing current variations according to a magnetization direction of the respective thin films. The MRAM has a high speed and low power consumption, and allows high integration density due to its unique properties of the magnetic thin film, and also performs a nonvolatile memory operation such as a flash memory.
The MRAM embodies a memory device by using a giant magneto resistive (GMR) or spin-polarized magneto-transmission (SPMT) phenomenon generated when the spin influences electron transmission.
The MRAM using the GMR phenomenon utilizes the fact that resistance remarkably varies when spin directions are different in two magnetic layers having a non-magnetic layer therebetween to embody a GMR magnetic memory device.
The MRAM using the SPMT phenomenon utilizes the fact that larger current transmission is generated when spin directions are identical in two magnetic layers having an insulating layer therebetween to embody a magnetic permeable junction memory device.
However, the MRAM research is still in its early stage, and concentrated more on the formation of multi-layer magnetic thin films, but less on the researches on a unit cell structure and a peripheral sensing circuit.
FIGS. 1a to 1i are cross-sectional diagrams illustrating sequential steps of a conventional method for manufacturing an MRAM, wherein both a cell region 100 and a peripheral circuit region 200 are shown.
Referring to FIG. 1a, a transistor (not shown) is formed on a semiconductor substrate (not shown), a ground line (not shown) connected to a source region (not shown) of the transistor is formed, and a first interlayer insulating film 11 planarizing the top surface of the resultant structure is formed.
A connection layer 13 which is a lower read layer connected to the drain region (not shown) of the transistor through the first interlayer insulating film 11 is formed.
Here, the connection layer 13 is composed of a metal.
Referring to FIG. 1b, a magnetic tunnel junction (MTJ) layer 15 is formed on the connection layer 13.
The MTJ layer 15 comprises a stacked structure of a semi-ferromagnetic layer, a pinned ferromagnetic layer and a free ferromagnetic layer.
Referring to FIG. 1c, a first photoresist film pattern 17 is formed on the MTJ layer 15.
Here, the first photoresist film pattern 17 is formed only on a portion of the MTJ layer 15 in the cell region 100 according to exposure and development processes using a MTJ cell mask (not shown).
Referring to FIGS. 1d and 1e, the MTJ layer 15 is etched using the first photoresist film pattern 17 as a mask to form a MTJ layer pattern 16. Thereafter, the first photoresist film pattern 17 is removed.
The etching process is a plasma etching process which damages the surface of the metal composing the connection layer 13. A defect layer 19 is formed due to this damage.
Referring to FIG. 1f, a second interlayer insulating film 21 planarizing the top surface of the resultant structure is formed.
Referring to FIG. 1g, a second photoresist film pattern 23 is formed on the second interlayer insulating film 21.
Here, the second photoresist film pattern 23 is formed according to exposure and development processes using a bit line contact mask (not shown) for forming a bit line which is an upper read layer. The second photoresist film pattern 23 exposes a portion of the second interlayer insulating film 21 on the MTJ layer pattern 16 of the cell region 100 and a portion of the second interlayer insulating film 21 on the connection layer 13 of the peripheral circuit region 200.
Referring to FIG. 1h, the second interlayer insulating film 21 is etched using the second photoresist film pattern 23 as a mask to form a first contact hole 25 and a second contact hole 27 respectively exposing the MTJ layer pattern 16 of the cell region 100 and the connection layer 13 of the peripheral circuit region 200.
At this time, the exposed portion 29 of the connection layer 13 has a high resistance due to the defective layer 19 at the bottom of the second contact hole 27. Accordingly, a resistance of a contact formed in a subsequent process is increased.
Referring to FIG. 1i, a bit line 31 which is an upper lead line connected to the MTJ layer pattern 16 and the connection layer 13 through the first and second contact holes 25 and 27 is formed. Here, an MTJ cell region is restricted to the region of the MTJ layer pattern 16 contacted by the bit line 31.
In the conventional method for manufacturing the MRAM, a defective layer is formed due to damages on the surface of the connection layer which is the lower read layer during the patterning process of the MTJ layer and the MTJ cell region is restricted to the region of the MTJ layer pattern contacted by the bit line which is the upper lead line.